Dynamic memory requires periodic refreshing to maintain the data stored in the memory. Though problems solved by the present invention apply to many types of dynamic memory, consider for this introduction a dynamic memory having an array of cells, each cell storing data as a charge on a cell capacitance.
Refreshing is accomplished by selecting a cell to refresh and recharging the cell capacitor. For memory with self refreshing capability, the act of selecting a cell to refresh is accomplished by refreshing circuits packaged with the memory. Refreshing circuits generally employ an address counter and clock oscillator for selecting a cell to refresh. Refreshing is performed in a so-called refresh cycle during which the address counter is incremented, a cell is selected, and a period of time is allowed for recharging the cell capacitor.
When the memory is performing self refreshing, refresh cycles are back to back, excluding other uses for the memory such as system read/write functions. Thus, when the system in which the memory exists requires use of the memory and the memory is currently performing self refreshing, the current refresh cycle must be terminated quickly so that the memory can respond to a read/write cycle as directed by the system.
When a system read/write cycle is begun soon after self refreshing has been interrupted, the cell selected during the last refresh cycle may not be properly refreshed. In an extreme case, the data stored in the cell is corrupted. Manufacturers of dynamic memory publish timing guidelines for systems designers including a time t.sub.RPS required between an interruption of self refreshing and the beginning of the earliest subsequent system read/write cycle. Systems designs, therefore, accommodate the time t.sub.RPS to avoid the possibility of improper refreshing and data corruption.
In the conventional dynamic memory capable of self refreshing, back to back refresh cycles are initiated in the absence of cycle by cycle signaling from the system to the memory. In addition, there is no signaling from the memory to the system indicating the beginning of a self refresh cycle. Consequently, there is no way to determine whether a given time is within t.sub.RPS for a particular memory device or a production lot of memory devices.
Thus, there remains a need for self refresh circuitry and methods that permit measurement of the shortest delay between interruption of self refreshing and the beginning of a system read/write cycle. In the absence of measurement, manufacturer's published timing guidelines include unnecessarily long delay allowances based on worst case conditions and margins for fabrication process variation. Without measurement, system designs must accommodate these conservative estimates of the delay resulting in poor system performance, slow system response, low system throughput, and generally limited system capability.